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Layout Recommendation:
Use the following general guidelines when designing
printed circuit boards. An example of the typical land
pattern for a DFN PI2007 and SO-8/PowerPak
MOSFET is shown in Figure 21 and Figure 22:
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It is best to connect the gate of the MOSFET to
the GATE pin of the controller with a short trace. A
gate resistor (R G ) is added to slow down the gate
turn off if needed.
The VC bypass capacitor should be located as
close as possible to the VC and SGND pins.
Place the PI2007 and VC bypass capacitor on the
same layer of the board. The VC pin and C VC
PCB trace should not contain any vias.
In an application where SGND is floating, a low
forward voltage drop Schottky diode has to be
added in parallel with C VC to protect the controller
during an input voltage short fault.
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PGND pin of the controller carries high peak
current during gate pull down, Connect PGND pin
with a wide trace to the C VC terminal at SGND.
Make sure that SGND trace and PGND trace
connect only at C VC terminal.
Connections from the SP and SN pins to the
MOSFET source and drain pins respectively
should be as short as possible
Connect all MOSFET source pins together with a
Figure 21: PI2007 controller and MOSFET layout
recommendation in a floating application.
wide trace to reduce trace parasitics and to
accommodate the high current input. Similarly,
connect all MOSFET Drain pins together with a
wide trace to accommodate the high current
output.
Figure 22: PI2007 controller and MOSFET layout
recommendation in a non-floating application
Picor Corporation ? picorpower.com
PI2007
Rev 1.3
Page 17 of 19
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